SparkEDA Inc target is to develop tools and methodologies for the most complete functional verification of the unit-level hardware designs.
Our block-level verification methodology enables quick and efficient way to achieve flawless functionality of complex control blocks.
Our flagship product, Panda Formal Verifier, implements new approach in combining simulation and formal techniques, achieving faster verification closure and making formal techniques easy and accessable for hardware designers.
ASTRA Productivity tool suite provides automated way to generate assertions and functional coverage code right from timing diagrams and state charts.
COVERIS functional coverage manager provides convenient means to implement and manage funcitonal coverage info in Verilog domain.